1. Field of the Invention
The present invention relates generally to a system for merging data from two different locations, both of which have been assigned the same address value.
2. Description of the Relevant Art
More particularly, the invention relates to a system for providing status information to a central processing unit (CPU) regarding removal of a floppy disk from a floppy disk drive and merging that information with data originating from a separate location. Still more particularly, the present invention relates to a system for combining floppy disk change data with data relating to the status of an integrated drive electronics ("IDE") hard drive controller in a system in which the floppy disk controller is located separately from the integrated drive electronics ("IDE") controller.
In prior personal computer systems, shown generally in FIG. 1, a floppy disk drive and integrated drive electronics for a hard drive typically were provided on the same physical card with a single controller that controlled the operation of each of these components. The controller typically connected to a central processing unit ("CPU") through an ISA bus or other bus structure. In these prior art systems, the controller included an 8-bit configuration register that performed various functions. One of the functions of that configuration register was to store and provide information to the CPU indicating whether the disk in the floppy drive had been changed. Such a change was indicated by the status of data bit D7 of that configuration register. Each time that the floppy disk was changed, bit D7 of the configuration register was set. The other data bits, D0-D6 of the controller configuration register were dedicated for IDE operations.
In accordance with the convention of these prior systems, the configuration register was assigned an address value of 3F7h. Consequently, when the CPU sought a read from the configuration register regarding either the status of the floppy disk change bit (bit D7), or of information relating to the IDE drive (bits D0-D6), the CPU would generate an address signal with a value of 3F7h to access this configuration register. In these prior systems, the address of the configuration register typically would be loaded into the CPU by the system BIOS (basic input/output system) during system initialization or "boot-up."
Recently, there has developed a trend in the computer industry to integrate components that were previously provided separately onto one or more integrated circuits. An example of such a computer system is shown, for example in FIG. 2. FIG. 2 is a block diagram of a computer system 10 including a microprocessor (CPU) 12, a CPU local bus 14 coupled to the microprocessor 12, and a local bus peripheral device 18 coupled to the CPU local bus 14. A PCI standard bus 20 is coupled to the CPU local bus 14 through a PCI bus bridge 22, and an ISA (Industry Standard Architecture) bus 24 is coupled to the CPU local bus 14 through ISA bus bridge 26. A PCI peripheral device 28 is shown coupled to the PCI bus 20, and an ISA peripheral device 30 is shown coupled to the ISA bus 24.
Microprocessor 12 is illustrative of, for example, a model 80486 microprocessor, and CPU local bus 14 is exemplary of an 80486-style local bus. The CPU local bus 14 includes a set of data lines D[31:0], a set of address lines A[31:0], and a set of control lines (not shown individually). Additional details regarding the various bus cycles and protocols of the 80486 CPU local bus 14 are described in numerous publications, and as such are not set forth in detail herein.
The PCI bus bridge 22 provides a standard interface between the CPU local bus 14 and the PCI bus 20. As such, PCI bus 20 bridge 22 orchestrates the transfer of data, address, and control signals between the two buses. PCI bus 20 is a high performance peripheral bus that supports burst-mode data transfers and that includes multiplexed data/address lines AD[31:0]. The PCI peripheral device 28 is illustrative of any PCI compatible peripheral device, such as a disk controller.
The ISA bus 24 of FIG. 2 supports the connection of ISA peripheral devices within the computer system 10. The ISA bus 26 coordinates the transfer of data, address, and control signals between the CPU local bus 14 and the ISA bus 24. Although the ISA bus is a relatively low performance bus, the inclusion of the ISA bus within the computer system permits various ISA peripheral devices to be connected within the system. A wide variety of such ISA compatible peripheral devices are available commercially.
The microprocessor 12, PCI bus bridge 22 and ISA bus bridge 26 have traditionally been fabricated on separate integrated circuit chips. A recent trend in computer systems has developed, however, in which the CPU core components are combined with a variety of peripheral devices on a single integrated processor chip. For example, the integrated processor chip may include a bus bridge to provide a high performance interface between an internal CPU local bus and an external bus, such as a PCI bus. By providing a high performance interface to an external PCI bus, relatively high performance characteristics can be achieved with respect to external data transfers.
In light of the recent trend toward greater system integration, it would be desirable to develop a system in which the floppy drive controller and the IDE drive controller are located separately thereby allowing one or both of these components to be incorporated into other integrated circuits. Separating these controllers therefore increases system flexibility. For example, as additional components are fabricated on a single integrated circuit, it would be desirable to include the floppy drive controller on such an integrated circuit that connects to the processor through the PCI bus. Similarly, it would be desirable to separately locate an IDE controller on either the ISA bus or the PCI bus, or in appropriate circumstances, to eliminate the IDE controller from the system.
To be compatible with prior BIOS systems, however, it is necessary that both the floppy drive controller and the IDE controller include a configuration register with an address value of 3F7h. The register in the floppy drive controller with an address value of 3F7h must include a data bit (D7) that provides status information regarding the removal of a disk from the floppy drive. Similarly, the configuration register in the IDE controller with an address value of 3F7h must include seven data bits (D0-D6) regarding the status and operation of the IDE drive.
If the IDE controller is located separately from the floppy controller, a problem therefore arises because these two units include two separate registers which are both addressed by the same value. Consequently, if the CPU is programmed by the system BIOS to make a read request to 3F7h to gather data bits D0-D7, the possibility arises that two different data signals will be driven on the system at the same time--one signal from the floppy controller providing bit D7, and a separate signal from the IDE controller providing bits D0-D6. As one skilled in the art will immediately understand, driving two signals on the system at the same time causes a problem with bus contention. Thus, while it is desirable to separate the operation of the floppy drive controller and the IDE drive controller for system flexibility, it is difficult to do so because of the desire for compatibility with prior BIOS systems.